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mp3908 current mode pwm controller with synchronous secondary gate drive mp3908 rev.0.9 www.monolithicpower.com 1 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. the future of analog ic technology description the mp3908 is a flexible current-mode pwm controller optimized for power-supply applications. the mp3908 features resistor- programmable dead-time control to optimize efficiency for a broad number of different configurations, and a synchronous secondary gate drive. the mosfet drivers are capable of driving >10a mosfets. it has an operational current of typically 270a and can accommodate off-line, telecom and non-isolated applications. under-voltage lockout, soft-start, slope compensation and peak current limiting are all included. in a boost application, with an output voltage of less than 28v, the current sense pin can connect directly to the drain of the external switch. this eliminates the requirement for an additional current sensing element and its associated efficiency loss. while designed for boost applications, the mp3908 can also be used for other topologies including forward, flyback and sepic. the 10v gate driver compliance minimizes the power loss of the external mosfet while allowing the use of a wide variety of standard threshold devices. an externally programmable delay following the turn off of the synchronous rectifier allows the incorporation of secondary side synchronous rectifier the mp3908 is available in space saving 10-pin msop package. features ? programmable dead-time ? synchronous secondary gate drive ? current mode control ? 10v mosfet gate drivers ? drives >10a mosfets ? soft-start ? cycle-by-cycle current limiting ? slope current compensation ? lossless current sense (v isense <28v) ? 50a shutdown current ? 270ua typical operating current ? 250khz constant frequency operation ? applicable to boost, sepic, flyback and forward topologies ? available in a 10-pin msop package applications ? poe pd power supplies ? tv ccfl power generation ? telecom isolated power ? brick modules ? off-line controller ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application mp3908 vcc css gnd en 9 6 10 4 3 1 7 8 5 2 isense sync main comp delay adj fb t1 60 65 70 75 80 85 90 95 0123456 efficiency (%) output current (a) efficiency vs. output current
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 2 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. package reference 1 2 3 4 5 10 9 8 7 6 top view part number* package temperature MP3908DK msop10 ?40 c to +85 c * for tape & reel, add suffix ?z (eg. MP3908DK?z) for rohs compliant packaging, add suffix ?lf (eg. MP3908DK?lf?z) absolute maxi mum ratings (1) vcc ............................................. ?0.3v to +10v vcc maximum current ............................ 30ma isense ....................................... ?0.3v to +28v fb .............................................. ?0.3v to +1.3v comp............................................ ?0.3v to +3v css, enable ............................... ?0.3v to +5v junction temperature...............................125 c lead temperature ....................................260 c storage temperature ..............?65c to +150 c recommended operating conditions (2) vcc current ................................. 1ma to 25ma operating temperature .............?40 c to +85 c thermal resistance (3) ja jc msop10 ................................ 150 ..... 65... c/w notes: 1) exceeding these ratings may damage the device. 2) the device is not guaranteed to function outside of its operating conditions. 3) measured on approximately 1? square of 1 oz copper. electrical characteristics v cc = 10v, t a = +25 c, unless otherwise noted. parameter symbol condition min typ max units vcc undervoltage lockout internal divider (i q ) 4.5 4.7 v vcc on/off voltage hysteresis 1 v shutdown current i s en/ss = 0v, v in = 9v 50 a quiescent current (operation) i q output not switching, v fb = 1v, v cc = 9v 270 320 a main gate driver impedance (sourcing) v cc = 9v, v gate = 5v 16 ? main gate driver impedance (sinking) v cc = 9v, i gate = 5ma 5.0 ? synchronous gate driver impedance (sourcing) v cc = 9v, v syncgate = 5v 16 ? synchronous gate driver impedance (sinking) v cc = 9v, i gate = 5ma 5.0 ? delay after synchronous gate r delay =100k ? 50 ns error amplifier transconductance v fb connected to v comp/run. force 10a to v comp/run . 0.26 0.38 0.46 ma/v maximum comp current sourcing and sinking 40 a error amplifier translator gain (4) a et 0.28 0.32 0.36 v/v switching frequency f s 220 260 300 khz thermal shutdown 150 c maximum duty cycle 76 81 86 % minimum on time t on 200 ns isense limit 165 190 215 mv fb voltage v fb 0.794 0.818 0.847 v fb bias current i fb current flowing out of part 50 na note: 4) guaranteed by design.
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 3 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. electrical characteristics (continued) v cc = 10v, t a = +25 c, unless otherwise noted. parameter symbol condition min typ max units isense bias current i sense current flowing out of part 50 na enable on threshold v en high-to-low 1.15 1.25 1.35 v enable hysteresis v en 50 mv soft start current i ss 4 a pin functions pin # name description 1 css capacitor soft start. a charging current of 5a is enabled when the enable pin is taken above 1.2v. the rise time of the capa citor allows output current soft start. full output current is allowed when the voltage is above 2.7v. 2 enable this pin serves two functions. below 0.6v , the part is in sleep mood, drawing 10a (typ). the second threshold of 1.2v can be used as a precise under-voltage lock out (uvlo) and enables full operation.. 3 comp compensation. 4 fb feedback forces this pin voltage to the 0.8v internal reference potential. do not allow this pin to rise above 1.2v in the application. 5 rdelay external resistor determines delay between the synchronous gate drive pin going low to the main gate drive going high. 6 isense current sense. do not connect this pin direct ly to the drain of the external mosfet if the voltage swing exceeds 27v in the particular application. during normal operation, this pin will sense the voltage across the exte rnal mosfet or sense resistor if one is used, limiting the peak inductor curr ent on a cycle-by-cycle basis. 7 gnd ground. 8 vcc input supply. decouple this pin as close as possible to the gnd pin. 9 main gate this pin drives the external main mosfet device. 10 sync gate this pin drives the external synchrono us mosfet device. the sync gate is disabled at the end of switching period if ma in gate is not turned on the next cycle.
mp3908 ? high efficiency boost controller mp3908 rev. 0.9 www.monolithicpower.com 4 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. operation enable vref = 0.8v 1.2v i max clamp slope compensation comp sgnd fb css enable ea translator optional filter ea oscillator delay internal bias rdelay 9.9v -- -- + + v out rsense driver pgnd rdson sensing main rdly isense sync gates off turn off i trp -- + s r q q s r q v in v cc v cc figure 1?functional block diagram the mp3908 uses a constant frequency, peak current mode architecture to regulate the feedback voltage. the operation of the mp3908 can be understood with the block diagram of figure 1. at the beginning of each cycle the main external n-channel mosfet is turned on, forcing the current in the inductor to increase. the current through the fet can either be sensed through a sensing resistor or across the external fet directly. this voltage is then compared to a voltage related to the comp/run node voltage. the voltage at the comp/run pin is an amplified voltage of the difference between the 0.8v reference and the feedback node voltage. when the voltage at the isense node rises above the voltage set by the comp/run pin, the external main fet is turned off and the synchronous fet, if used, is turned on. the inductor current then flows to the output capacitor through the schottky diode. the inductor current is controlled by the comp/run voltage, which itself is controlled by the output voltage. the peak inductor current is internally limited by the i max clamp voltage that limits the voltage applied to the i trp comparator input. thus the output voltage controls the inductor current to satisfy the load. this current mode architecture improves transient response and control loop stability over a voltage mode architecture.
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 5 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. application information component selection setting the output voltage set the output voltage by selecting the resistive voltage divider ratio. if we use 10k ? for the low- side resistor (r2) of the voltage divider, we can determine the high-side resistor (r1) by the equation: ref ref out v ) v v ( 2 r 1 r ? = where v out is the output voltage. for r2=10k ? , v out =25v and v ref =0.8v, then r1=301k ? . an external resistor tied from the r delay pin to ground programs an internal time delay circuit that sets a delay from the turn off of the synchronous mosfet drive pin output to the turn on of the main mosfet drive pin output. this delay is adjustable to program the required time interval required by the circuitry to turn off the synchronous mosfet from the time that the synchronous output drive signal goes low. this path may include active devices as well as an isolating transformer used to electrically isolate the secondary side output. efficiency losses can be quite significant if an overlap occurs between the main and synchronous switching mosfets if the delay is not carefully determined and accounted for. the r delay pin has an internal resistance of approximately 50kohms that should be added to any external resistance used to approximate the delay interval. shorting the pin directly to ground will result in approximately 30nsec delay as a result of this internal resistance. a graph is provided in the applications section of this data sheet to illustrate the typical delay time generated versus the resistor value selected selecting the inductor and current sensing resistor the inductor is required to transfer the energy between the input source and the output capacitors. a larger value inductor results in less ripple current that results in lower peak inductor current, and therefore reduces the stress on the power mosfet. however, the larger value inductor has a larger physical size, higher series resistance, and/or lower saturation current. a good rule of thumb is to allow the peak-to-peak ripple current to be approximately 30-50% of the maximum input current. make sure that the peak inductor current is below 80% of the ic?s maximum current limit at the operating duty cycle to prevent loss of regulation. make sure that the inductor does not saturate under the worst-case load transient and startup conditions. the required inductance value can be calculated by : i f v ) v - (v v l sw out in(min) out ) min ( in ? = = ) min ( in ) max ( load out ) max ( in v i v i ( ) ) max ( in i % 50 % 30 i ? = ? where i load (max) is the maximum load current, ? i is the peak-to-peak inductor ripple current and is the efficiency. for a typical design, boost converter efficiency can reach 85%~95%. for v in (min) =10v, v out =25v, i load (max) =2a, the ripple percentage being 30%, =95% and f sw =330khz, then l=10h. in this case, use a 8.8h inductor (i.e. sumida cdrh127/ldnp- 100mc). the switch current is usually used for the peak current mode control. in order to avoid hitting the current limit, the voltage across the sensing resistor r sense should be less than 80% of the worst case current limit voltage, 200mv. ) peak ( l sense i 2 . 0 8 . 0 r = where i l (peak) is the peak value of the inductor current.
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 6 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. for i l (peak) =5.3a, r sense =30m ? . in cases where the r ds(on) of the power mosfet is used as the sensing resistor, be sure that the r ds(on) is lower than the value calculated above, 30m ? another factor to take into consideration is the temperature coefficient of the mosfet r ds(on) . as the temperature increases, the r ds(on) also increases.. device vendors will usually provide an r ds(on) vs. temperature curve and the temperature coefficient in the datasheet. generally, the mosfet on resistance will double from 25 c to 125 c. selecting the input capacitor an input capacitor (c1) is required to supply the ac ripple current to the inductor, while limiting noise at the input source. a low esr capacitor is required to keep the noise to the ic at a minimum. ceramic capacitors are preferred, but tantalum or low-esr electrolytic capacitors may also suffice. the capacitance can be calculated as: sw in(ripple) 1 f v 8 i c ? ? where ? i is the peak-to-peak inductor ripple current and ? v in(ripple) is the input voltage ripple. when using ceramic capacitors, take into account the vendor specified voltage and temperature coefficients for the particular dielectric being used. for example, 2.2uf capacitance is sufficient to achieve less then 1% input voltage ripple. meanwhile, it requires an adequate ripple current rating. use a capacitor with rms current rating greater than the inductor ripple current (see selecting the inductor to determine the inductor ripple current). in addition, a smaller high quality ceramic 0.1 f~1f capacitor may be placed to absorb the high frequency noise. if using this technique, it is recommended that the larger capacitor be a tantalum or electrolytic type. selecting the output capacitor typically, a boost converter has significant output voltage ripple because the current through the output diode is discontinuous. during the diode off state, all of the load current is supplied by the output capacitor. low esr capacitors are preferred to keep the output voltage ripple to a minimum. the characteristics of the output capacitor also affect the stability of the regulation control system. ceramic, tantalum or low esr electrolytic capacitors are recommended. in the case of ceramic capacitors, the impedance of the capacitor at the switching frequency is dominated by the capacitance, and so the output voltage ripple is mostly independent of the esr. the output voltage ripple is estimated to be: sw load out in ripple f 2 c i v v - 1 v ? ? ? ? ? ? ? ? where v ripple is the output ripple voltage, v in and v out are the dc input and output voltages respectively, i load is the load current, f sw is the switching frequency and c2 is the output capacitor. in the case of tantalum or low-esr electrolytic capacitors, the esr dominates the impedance at the switching frequency. therefore, the output ripple is calculated as: in out esr load ) pk _ pk ( ripple v v r i v where r esr is the equivalent series resistance of the output capacitors. for the application shown in page 1, use ceramic capacitor as an example. for v in(min) =10v, v out =25v, i load(max) =2a, and v ripple =1% of the output voltage, the capacitance c 2 =14.5f. please note that the ceramic capacitance could dramatically decrease as the voltage across the capacitor increases. as a result, larger capacitance is recommended. in this example, place four 4.7f ceramic capacitors in parallel. the voltage rating is also chosen as 50v. in the meantime, the rms current rating of the output capacitor needs to be sufficient to handle
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 7 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. the large ripple current. the rms current is given by: () 2 load out in ) max ( in load 2 ) max ( in ) rms ( ripple i v v i i 2 i i + ? inmax 2 nmax i ) rms ( ripple i 5 . 0 i ) d 1 ( d i < ? for i in(max) =5.3a, i load =2a, v in =12v and v out =25v, i ripple(rms) =2.64a. make sure that the output capacitor can handle such an rms current. in addition, a smaller high quality ceramic 0.1 f~1uf capacitor needs to be placed at the output to absorb the high frequency noise during the commutation between the power mosfet and the output diode. basically, the high frequency noise is caused by the parasitic inductance of the trace and the parasitic capacitors of devices. the ceramic capacitor should be placed as close as possible to the power mosfet and output diode in order to minimize the parasitic inductance and maximize the absorption. selecting the power mosfet the mp3908 is capable of driving a wide variety of n-channel power mosfets. the critical parameters of selection of a mosfet are: 1. maximum drain to source voltage, v ds(max) 2. maximum current, i d(max) 3. on-resistance, r ds(on) 4. gate source charge q gs and gate drain charge q gd 5. total gate charge, q g ideally, the off-state voltage across the mosfet is equal to the output voltage. considering the voltage spike when it turns off, v ds(max) should be greater than 1.5 times of the output voltage. the maximum current through the power mosfet happens when the input voltage is minimum and the output power is maximum. the maximum rms current through the mosfet is given by max in(max) ) max ( rms d i i = where: out ) min ( in out max v v v d ? the current rating of the mosfet should be greater than 1.5 times i rms, the on resistance of the mosfet determines the conduction loss, which is given by: k r i p (on) ds 2 rms cond = where k is the temperature coefficient of the mosfet. if the r ds(on) of the mosfet is used as the current sensing resistor, make sure the voltage drop across the device does not exceed the current limit value of 190mv. the switching loss is related to q gd and q gs1 which determine the commutation time. q gs1 is the charge between the threshold voltage and the plateau voltage when a driver charges the gate, which can be read in the chart of v gs vs. q g of the mosfet datasheet. q gd is the charge during the plateau voltage. these two parameters are needed to estimate the turn on and turn off loss. sw in ds plt dr g gd sw in ds th dr g gs1 sw f i v v v r q f i v v v r q p ? + ? = where v th is the threshold voltage, v plt is the plateau voltage, r g is the gate resistance, v ds is the drain-source voltage. please note that the switching loss is the most difficult part in the loss estimation. the formula above provides a simple physical expression. if more accurate estimation is required, the expressions will be much more complex. for extended knowledge of the power loss estimation, readers should refer to the book ?power mosfet theory and applications? written by duncan a. grant and john gowar. the total gate charge, q g , is used to calculate the gate drive loss. the expression is sw dr g dr f v q p = where v dr is the drive voltage. for the application in page 1, a fds6630 or equivalent mosfet is chosen. read from the datasheet: r ds(on) =28m ? , k = 0.5, q gd =0.9nc,
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 8 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. q gs1 =1nc, v th =1.7v, v plt =3v and q g =5nc @ 10v. the mp3908 has its gate driving resistance of around 20 ? at v dr =10v and v gate = 5v. based on the loss calculation above, the conduction loss is around 0.629w. the switching loss is around 0.171w, and the gate drive loss is 0.015w. selecting the output diode the output rectifier diode supplies current to the inductor when the mosfet is off. to reduce losses due to diode forward voltage and recovery time, use a schottky diode. the diode should be rated for a reverse voltage greater than the output voltage used. considering the voltage spike during the commutation period, the voltage rating of the diode should be set as 1.5 times the output voltage. for high output voltages (150v or above), a schottky diode might not be practical. a high-speed ultra-fast recovery silicon rectifier is recommended. observation of the boost converter circuit shows that the average current through the diode is the average load current, and the peak current through the diode is the peak current through the inductor. the average current rating must be greater than 1.5 times of the maximum load current, and the peak current rating must be greater than the peak inductor current. for the application in page 1, a vishay ss16 schottky diode or equivalent part is chosen. boost converter: compensation design the output of the transconductance error amplifier (comp) is used to compensate the regulation control system. the system uses two poles and one zero to stabilize the control loop. the poles are f p1 , which is set by the output capacitor (c2) and load resistance and f p2 , which starts from origin. the zero (f z1 ) is set by the compensation capacitor (c3) and the compensation resistor (r3). these parameters are determined by the equations: load 1 p r c2 1 f = 3 r c3 2 1 f 1 z = where r load is the load resistance. the dc mid-band loop gain is: sense 2 out et ref load in ea vdc r v a 3 r v r v g 5 . 0 a = where v ref is the voltage reference, 0.8v. a et is the gain of error amplifier translator and g ea is the error amplifier transconductance. the esr zero in this example locates at very high frequency. therefore, it is not taken into design consideration. there is also a right-half-plane zero (f rhpz ) that exists in continuous conduction mode (inductor current does not drop to zero on each cycle) step-up converters. the frequency of the right half plane zero is: 2 2 out load in rhpz v l 2 r v f = the right-half-plane zero increases the gain and reduces the phase simultaneously, which results in smaller phase margin and gain margin. the worst case happens at the condition of minimum input voltage and maximum output power. in order to achieve system stability, f z1 is placed close to f p1 to cancel the pole. r3 is adjusted to change the voltage gain. make sure the bandwidth is about 1/10 of the lower one of the esr zero and the right-half-plane zero. r3 c3 2 1 r c2 1 load = et in ref ea sense c out a v v g r f 2 c 2 v 3 r 2 = based on these equations, r3 and c3 can be solved. for the application in page 1, f p1 = 1.35khz, esr zero is much higher than the switching frequency and f rhpz =45.8khz. set f z1 to 3.18khz and make the crossover frequency 8.5khz, then r3=5k ? and c3=10nf. choose 5k ? and 10nf.
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 9 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. in cases where the esr zero is in a relatively low frequency region and results in insufficient gain margin, an optional capacitor (c5) (shown in flat page) should be added. then a pole, formed by c5 and r3, should be placed at the esr zero to cancel the adverse effect. f esrz r3 2 1 5 c = layout consideration high frequency switching regulators require very careful layout for stable operation and low noise. keep the high current path as short as possible between the mosfet drain, output diode, output capacitor and gnd pin for minimal noise and ringing. the v cc capacitor must be placed close to the vcc pin for best decoupling. all feedback components must be kept close to the fb pin to prevent noise injection on the fb pin trace. the ground return of the input and output capacitors should be tied closed to the gnd pin. see the mp3908 demo board layout for reference.
mp3908 ? high efficiency boost controller mp3908 rev.0.9 www.monolithicpower.com 10 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. typical application circuits mp3908 delay en css comp fb sync isense gnd vcc 5 7 8 9 6 10 4 3 2 1 vin 36v to 72v pgnd en d4 11v q8 r2 300k r4 82.5k r3 20k r5 10k r7 910k c4 ns c5 10nf r1 1k q1 2n7002 r32 0 r6 51k r8 30k d1 200v r11 499k r12, 5 c8 330pf r13, 1k r31 ns r14 0 d3 c7 4.7uf vcc r9 30k r10 30k np1 np2 r20 10 r21 976 r25 10k r26 33.2k r28 10k q7 tlv431/1.24v r27 10k q6 2n3904 r29 ns c16 10nf r24 ns c17 470pf vout 5v@5a gnd r23 1.5k r30 100k c15 33nf u2 pc817b ns t1 8:1:4 t2 r34, 330 d5 r18, 5 r19 3k d7 15v q5 d6 1 23 3 7, 8, 9 10, 11, 12 2 1 5 4 r35 1k vcc vcc q3 ns d8 ns r33 0 r17 200 r16 0.05 q2 si7450 d2 r15 470k c18 1000pf/2000v r22 204 q4 ns sync sync + figure 2?mp3908 isolated synchronous flyback application
mp3908 ? high efficiency boost controller notice: the information in this document is subject to change wi thout notice. please contact m ps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp3908 rev. 0.9 www.monolithicpower.com 11 8/29/2008 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2008 mps. all rights reserved. package information msop10 bottom view 0.030(0.75) 0.037(0.95) 0.043(1.10)max 0.002(0.05) 0.006(0.15) front view 0.004(0.10) 0.008(0.20) side view gauge plane 0.010(0.25) 0.016(0.40) 0.026(0.65) 0 o -6 o seating plane pin 1 id (note 5) 0.114(2.90) 0.122(3.10) 0.187(4.75) 0.199(5.05) 1 5 6 10 0.007(0.18) 0.011(0.28) 0.0197(0.50)bsc 0.114(2.90) 0.122(3.10) top view note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusion or gate burr. 3) package width does not include interlead flash or protrusion. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) pin 1 identification has the half or full circle option. 6) drawing meets jedec mo-817, variation ba. 7) drawing is not to scale. recommended land pattern 0.012(0.30) 0.0197(0.50)bsc 0.181(4.60) 0.040(1.00)

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